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MoBL
CY62148V MoBLTM
512K x 8 MoBL Static RAM
Features
* Low voltage range: -- 2.7V-3.6V * Ultra low active power * Low standby power * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power The device can be put into standby mode when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII, and a 32-pin SOIC package.
Functional Description
The CY62148V is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling.
Logic Block Diagram
Data in Drivers
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512K x 8 ARRAY
CE WE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A10 A11 A12 A13 A14 A15 A16 A17 A18
OE
62148V-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 March 23, 2000
CY62148V MoBLTM
Pin Configurations
TSOPII/SOIC Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
FBGA Top View
1 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 A0 I/O 4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 A18 CE A11 A17 A16 A12 A15 A13 2 A1 A2 3 NC WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 A B C D E F G H
62148V-2
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................... 55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[1] ................................ -0.5V to V CC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial) Product Min. CY62148V 2.7V VCC Range Typ.[2] 3.0V Max. 3.6V Speed 70 ns Operating (ICC) Typ.[2] 7 Maximum 15 mA Ty.p[2] 2 A Standby (ISB2) Maximum 20 A
Notes: 1. VIL(min.) = -2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
2
CY62148V MoBLTM
Electrical Characteristics Over the Operating Range
CY62148V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, (f = fMAX = 1/tRC) CMOS Levels VCC = 3.6V Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 Typ.[2] Max. Unit V V V V A A mA
IOUT = 0 mA, f = 1 MHz CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs CE > V CC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 L VCC = 3.6V LL
1
2 100
mA A
ISB2
1 2
50 20
A A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Thermal Resistance
Description Thermal Resistance (Junction to Ambient)
[3]
Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board
Symbol JA JC
Others TBD TBD
BGA TBD TBD
Units C/W C/W
Thermal Resistance[3] (Junction to Case)
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62148V MoBLTM
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE
62148V-3
ALL INPUT PULSES VCC Typ R2 10% GND
Rise Time: 1 V/ns
90%
90% 10%
Fall time: 1 V/ns
62148V-4
Equivalent to:
THEVENIN EQUIVALENT R TH V TH
OUTPUT
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75V
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.0V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V No input may exceed VCC+0.3V L/ LL Conditions Min. 1.0 0.2 Typ.[2] Max. 3.6 5.5 Unit V A A
tCDR[3] tR[4]
Chip Deselect to Data Retention Time Operation Recovery Time
0 tRC
ns ns
Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 s or stable at VCC(min.) > 10 s.
Data Retention Waveform
DATA RETENTION MODE VCC 1.0V tCDR CE
62148V-5
VDR > 1.0 V
1.0V tR
4
CY62148V MoBLTM
Switching Characteristics Over the Operating Range[5]
(2.7V-3.6V Operation) Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE CYCLE[8, 9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[6, 7] [6]
Description
Min.
Max.
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[6]
70 70 10 70 35 5 25 10 25 0 70 70 60 60 0 0 50 30 0 25 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z[7 ]
[6] [6, 7]
CE HIGH to High Z
CE LOW to Power-Up CE HIGH to Power-Down
WE HIGH to Low Z
Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified I OL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. t HZOE, tHZCE, and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
5
CY62148V MoBLTM
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
62148V-6
Read Cycle No. 2
CE
[11, 12]
tRC
tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB
62148V-7
tHZOE tHZCE DATA VALID
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[8, 13, 14]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 15 tHZOE
Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN VALID
62148V-8
6
CY62148V MoBLTM
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[8, 13, 14]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O
[9, 14]
tSCE
tHA
tHD
62148V-9
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 15 tHZWE DATAIN VALID
tHD
tLZWE
62148-10
7
CY62148V MoBLTM
Typical DC and AC Characteristics
1.4 1.2 1.0 ISB (A) ICC 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 45 40 35 30 25 20 15 10 1.0 3.7 2.8 1.9 SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 1.0 1.9 2.8 3.7
SUPPLY VOLTAGE (V)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Mode Deselect/Power-Down Read Write Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
8
CY62148V MoBLTM
Ordering Information
Speed (ns) 70 Ordering Code CY62148VLL-70BAI CY62148VLL-70ZI CY62148VLL-70SI Document #: 38-00646-C Package Name BA37 ZS32 S34 32-Lead TSOPII 32-Lead 450 mil. molded SOIC Package Type 36-Ball Fine Pitch BGA Operating Range Industrial
Package Diagrams
36-Ball (7.00 mm x 8.5 mm x 1.5 mm) Thin BGA BA37
51-85105-A
9
CY62148V MoBLTM
Package Diagrams (continued)
32-Lead (450 MIL) Molded SOIC S34
10
CY62148V MoBLTM
Package Diagrams (continued)
32-Lead TSOP II ZS32
51-85095
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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